Την Τετάρτη 16/05/2018 στις 14:00, στην αίθουσα 137.Π.39 στο Κτήριο Επιστημών, στην Πολυτεχνειούπολη, θα δοθεί ομιλία με τίτλο "Communications Hardware In The Post-Happy-Scaling Era" από τον κ. Αλέξιο Μπαλατσούκα-Στίμμινγ, Μεταδιδακτορικό Ερευνητή στο EPFL|École polytechnique fédérale de Lausanne, Ελβετία.
Περίληψη της ομιλίας:
During the so-called happy scaling era of integrated circuits, the increasing transistor count per unit area and the increasing energy-efficiency were able to offset the ever-increasing complexity of communications and digital signal processing algorithms. Unfortunately, the gains from circuit technology scaling have slowed down significantly in the last few years. In this talk, I will discuss some ways to ensure that the progress of the last decades is maintained, ranging from classical algorithm/hardware co-design to more interdisciplinary approaches. More specifically, I will first discuss the hardware implementation of successive cancellation list decoding and successive cancellation flip decoding of polar error-correcting codes (ECC), which were recently included in the next-generation 5G standard for wireless communications. I will then examine the use of approximate computing techniques to increase the throughput and energy-efficiency of ECC decoders. Finally, I will present the application of tools from information theory and machine learning to the design of Terabit/s ECC decoders and non-linear self-interference cancellation in full-duplex radios, respectively.
Dr. Alexios Balatsoukas-Stimming received the Diploma and MSc degrees in Electronics and Computer Engineering from the Technical University of Crete, Chania, Greece, in 2010 and 2012, respectively, and a PhD in Computer and Communications Sciences from the École polytechnique fédérale de Lausanne (EPFL), Switzerland, in 2016. He spent one year at the European Laboratory for Particle Physics (CERN) as a Marie Skłodowska-Curie postdoctoral fellow and he is currently a postdoctoral researcher in the Telecommunications Circuits Laboratory at EPFL. His research interests include VLSI circuits for communications, error correction coding theory and practice, as well applications of approximate computing and machine learning to signal processing for communications.