Ημερολόγιο Εκδηλώσεων

Περιγραφή:
ΠΟΛΥΤΕΧΝΕΙΟ ΚΡΗΤΗΣ
Σχολή Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών
Πρόγραμμα Προπτυχιακών Σπουδών

ΠΑΡΟΥΣΙΑΣΗ ΔΙΠΛΩΜΑΤΙΚΗΣ ΕΡΓΑΣΙΑΣ

Κωσταρέλος Φώτης

με θέμα

Λιγότερο ίσον περισσότερο: Αυξάνοντας το Πεδίο Δράσης του Ενσωματωμένου Λογικού Αναλυτή της Xilinx με την Χρήση Αλγόριθμου Συμπίεσης

Less is more: Increasing the Scope of the Xilinx Integrated Logic Analyzer with Compression

Δευτέρα 18 Ιουνίου 2018, 12 π.μ.
Αίθουσα 145.Π58, Κτίριο Επιστημών, Πολυτεχνειούπολη

Εξεταστική Επιτροπή
Καθηγητής Πνευματικάτος Διονύσιος (επιβλέπων)
Καθηγητής Παπαευσταθίου Ιωάννης
Καθηγητής Δόλλας Απόστολος

Abstract

Complexity and size of large-scale hardware designs is gradually increasing due to tool's-automation and the use of multiple IPs in the same design. Therefore efficiently debugging the entire system seems to be very hard, while hardware designers have to deal with finding and addressing the various vulnerable regions within these complex systems. For that purpose different modules and wires need to be monitored. Vivado's ILA (Integrated Logic Analyzer) IP is an advanced tool provided by vendor that is used to accomplish this mission. Every design under construction which needs testing can easily embed this IP pre-synthesis or post-synthesis. Despite the advantages that a user gets, the ILA has some defects e.g memory constraints. Hence an improvement to the memory management would be beneficial. How we are going to use the available resources is crucial. So, a lossless data compression module, placed between the ILA and a signal inside a design, is proposed. This technique implicitly will offer a gain in space, thing that it's going to be more clear later on. In order to select an algorithm for the compression module, we had 2 criteria to consider, first the Compression Ratio(CR) and second the needs of real-time debugging. From a search with these directions came that LZW is the desired algorithm. LZW stands for Lempel–Ziv–Welch, an improved implementation of the LZ78 algorithm. Thus, the main contribution of this thesis is an IFT(Integrated-Logic-Analyzer Facilitation Technique), a novel framework for hardware debugging that utilizes the LZW compression algorithm and exploits the debugging capabilities of the ILA cores. The tools used for the deployment of the proposed framework were: High Level Synthesis(HLS) Vivado and the Software Developement Kit(SDK)